Evaluating architecture-level optimization in packet processing caches

Evaluating Associativity in CPU Caches

High Level Synthesis for Packet Processing Pipelines

High Level Synthesis for Packet Processing Pipelines

Efficient Packet Classification with Digest Caches

In this paper, we propose a digest cache-based algorithm for efficient packet classification in network devices. The digest cache-based algorithm classifies packets by using a hash of the flow identifier allowing for smaller sized cache entries at the expense of a small amount of packet misclassification. Experimentation will show that our technique is superior to previous Bloom filter based de...

Automated Organization of Caches Architecture

We consider the case of a multi-discipline company distributed in several sites. These sites are linked with a sufficiently dimensioned Intranet which allows a good quality of service. We use caches to increase the comfort of the users for an external connectivity to Internet. These caches are organized so as to cooperate and so to optimize performances. The objective of this proposal is to use...

A Programmable State Machine Architecture for Packet Processing

The Internet is expanding rapidly and constantly adding new protocols and features. To shorten the design cycle, many companies have adopted a common hardware platform for a variety of products. In these products, specialized packet processors tailored for packet processing handle multiple protocols and feature changes. A packet processor usually incorporates multiple RISC engines that are conf...